module trans_data_buf #(
    parameter SYNC1 = 10'b1010_1010_10, //preamble---前导�?
    parameter SYNC2 = 10'b1010_1010_11
  )
  (
    input						rst,
    input						clk_10M,
    input						clk_100M,
    input						tx_nce,
    input						tx_nwe,
    input			[8:0]		tx_addr,
    input			[8:0]		tx_data,
    input						tx_noe,
    output			[8:0] 		tx_rd_data,
    output	reg[1:0]			tx_rdy,
    output						tx_out
  );

  reg				tx_vld;
  reg				tx_done;
  reg  				ki;

  reg				ntx_nce_r;

  reg				tx_nwe_r;
  reg				ntx_nwe_r;
  reg				nntx_nwe_r;
  reg            tx_nwe_fg;



  reg	[8:0]	addr_ram_a;
  reg	[8:0] tx_data_r;


  reg			addr_b_ab = 0;
  reg   [7:0] addr_b;

  wire  [8:0] q_b;
  reg			clr_b;
  reg   [7:0] trans_len;
  reg	[7:0] tx_data_b;

  wire	[8:0] addr_ram_b;

  assign      addr_ram_b = {addr_b_ab,addr_b};

  reg   [3:0] trans_buf_st;

  always@(posedge clk_100M or posedge rst)
    if (rst)
    begin
      ntx_nce_r	  <= 1'b0;
      addr_ram_a	 <= 0;
      tx_data_r	  <= 0;
      tx_nwe_r		  <= 1'b0;
      ntx_nwe_r	  <= 1'b1;
      nntx_nwe_r	 <= 1'b0;
      tx_nwe_fg	  <= 1'b0;
    end
    else
    begin
      ntx_nce_r		 <= !tx_nce;
      addr_ram_a	 <= tx_addr;   //ping pong buffer, a port
      tx_data_r	  <= tx_data;
      tx_nwe_r		  <= tx_nwe;
      ntx_nwe_r	  <= ~tx_nwe_r;
      nntx_nwe_r	 <= ~ntx_nwe_r;
      tx_nwe_fg	  <= ntx_nce_r&ntx_nwe_r&nntx_nwe_r;  //falling edge
    end

  always@(posedge clk_10M or posedge rst)
    if (rst)
    begin
      addr_b_ab		   <= 0;   //ab ---ping pong
      addr_b			     <= 255;
      tx_data_b		   <= 0;
      clr_b				     <= 1'b0;
      tx_rdy			     <= 0;
      tx_vld			     <= 1'b0;
      tx_done			    <= 1'b0;
      trans_buf_st	 <= 0;
    end
    else
    case(trans_buf_st)
      0:
      begin
        addr_b_ab		   <= 0;
        addr_b			     <= 255;
        tx_data_b		   <= 0;
        clr_b				     <= 1'b0;
        tx_rdy			     <= 0;
        tx_vld			     <= 1'b0;
        tx_done			    <= 1'b0;
        trans_buf_st	 <= 1;
      end
      1:
      begin
        clr_b				     <= 1'b0;
        trans_buf_st	 <= 2;
      end
      2:
      begin
        if (q_b[8])
        begin
          trans_buf_st	 <= 3;
          addr_b			     <= 0;

        end
        else
        begin
          trans_buf_st	 <= 1;
          addr_b_ab	    <= ~addr_b_ab;
          if (addr_b_ab)
            tx_rdy[1]			 <= 1'b1;
          else
            tx_rdy[0]			 <= 1'b1;

        end

      end
      3:
      begin
        tx_vld		      <= 1'b1;
        tx_done		     <= 1'b0;
        ki				        <= 1'b1;
        tx_data_b	    <= 8'hbc;  //K28.5  ----frame start
        trans_len		   <= q_b[7:0];
        addr_b			     <= addr_b+1'b1;
        trans_buf_st	 <= 4;
      end
      4:
      begin
        trans_len		 <= trans_len-1'b1;
        addr_b			   <= addr_b+1'b1;
        tx_vld		    <= 1'b1;
        tx_done		   <= 1'b0;
        ki				      <= 1'b0;
        tx_data_b	  <= q_b[7:0];
        if (trans_len == 0)
        begin
          trans_buf_st	 <= 5;
          ki				        <= 1'b1;
          tx_data_b	< = 8'h3c;  //K28.1    001_11100 = 0011_1100
        end
      end
      5:
      begin
        tx_vld		     <= 1'b0;
        tx_done		    <= 1'b1;
        ki				       <= 1'b0;
        tx_data_b	   <= 0;
        addr_b			    <= 255;
        clr_b				    <= 1'b1;
        trans_buf_st <= 6;
      end
      6:
      begin
        tx_done		 <= 1'b0;
        clr_b				 <= 1'b0;

        addr_b_ab	   <= ~addr_b_ab;
        trans_buf_st <= 1;
      end

      default:
        trans_buf_st <= 0;
    endcase

  trans_ram trans_ram_inst (
              .address_a 	(addr_ram_a),
              .address_b 	(addr_ram_b),
              .clock_a 	(clk_100M),
              .clock_b 	(clk_10M),
              .data_a 		(tx_data_r),
              .data_b 		(9'b0),
              .wren_a 		(tx_nwe_fg),
              .wren_b 		(clr_b),
              .q_a 			(tx_rd_data),
              .q_b 			(q_b)
            );

  trans_data
    #(
      .SYNC1(SYNC1),   //preamble---前导�?
      .SYNC2(SYNC2)
    )
    trans_data_inst
    (
      .rst			(rst),
      .clk_10M		(clk_10M),
      .clk_100M		(clk_100M),
      .tx_vld		(tx_vld),
      .tx_done		(tx_done),
      .ki			(ki),
      .tx_data		(tx_data_b),
      .tx_out		(tx_out)
    );

endmodule
